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? semiconductor components industries, llc, 2004 january, 2004 ? rev. 6 1 publication order number: mc33171/d mc33171, mc33172, mc33174 single supply 3.0 v to 44 v, low power operational amplifiers quality bipolar fabrication with innovative design concepts are employed for the mc33171/72/74 series of monolithic operational amplifiers. these devices operate at 180 a per amplifier and offer 1.8 mhz of gain bandwidth product and 2.1 v/ s slew rate without the use of jfet device technology. although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage includes ground potential (v ee ). with a darlington input stage, these devices exhibit high input resistance, low input offset voltage and high gain. the all npn output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink ac frequency response. the mc33171/72/74 are specified over the industrial/ automotive temperature ranges. the complete series of single, dual and quad operational amplifiers are available in plastic as well as the surface mount packages. ? low supply current: 180 a (per amplifier) ? wide supply operating range: 3.0 v to 44 v or 1.5 v to 22 v ? wide input common mode range, including ground (v ee ) ? wide bandwidth: 1.8 mhz ? high slew rate: 2.1 v/ s ? low input offset voltage: 2.0 mv ? large output voltage swing: ?14.2 v to +14.2 v (with 15 v supplies) ? large capacitance drive capability: 0 pf to 500 pf ? low total harmonic distortion: 0.03% ? excellent phase margin: 60 ? excellent gain margin: 15 db ? output short circuit protection ? esd diodes provide input protection for dual and quad ? pb?free package may be available. the g?suffix denotes a pb?free lead finish pdip?8 p suffix case 626 1 8 so?8 d, vd suffix case 751 1 8 pdip?14 p, vp suffix case 646 1 14 so?14 d, vd suffix case 751a 1 14 see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information tssop?14 dtb suffix case 948g see general marking information in the device marking section on page 9 of this data sheet. device marking information 1 14 http://onsemi.com
mc33171, mc33172, mc33174 http://onsemi.com 2 single 7 6 5 (single, top view) (top view) offset null 1 2 3 4 8 7 6 5 noninv. input v ee nc v cc output offset null inv. input v ee inputs 1 inputs 2 output 2 output 1 v cc 1 2 3 4 8 + - + - - + 2 1 quad inputs 1 output 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 (top view) 1 2 3 4 5 6 78 9 10 11 12 13 14 4 23 1 - + - + + - + - pin connections dual q1 q3 q4 q5 q6 q7 v cc q2 r1 c1 r2 q9 q10 q8 - + inputs q11 q17 d2 r6 r7 q18 c2 d3 r8 output q19 q16 q15 q14 q13 q12 d1 r3 r4 r5 current limit v ee /gnd offset null (mc33171) bias figure 1. representative schematic diagram (each amplifier)
mc33171, mc33172, mc33174 http://onsemi.com 3 maximum ratings rating symbol value unit supply voltage v cc /v ee 22 v input differential voltage range v idr (note 1) v input voltage range v ir (note 1) v output short circuit duration (note 2) t sc indefinite sec operating ambient temperature range t a (note 3) c operating junction temperature t j +150 c storage temperature range t stg ?65 to +150 c dc electrical characteristics (v cc = +15 v, v ee = ?15 v, r l connected to ground, t a = +25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (v cm = 0 v) v cc = +15 v, v ee = ?15 v, t a = +25 c v cc = +5.0 v, v ee = 0 v, t a = +25 c v cc = +15 v, v ee = ?15 v, t a = t low to t high (note 3) v io ? ? ? 2.0 2.5 ? 4.5 5.0 6.5 mv average temperature coefficient of offset voltage v io / t ? 10 ? v/ c input bias current (v cm = 0 v) t a = +25 c t a = t low to t high (note 3) i ib ? ? 20 ? 100 200 na input offset current (v cm = 0 v) t a = +25 c t a = t low to t high (note 3) i io ? ? 5.0 ? 20 40 na large signal voltage gain (v o = 10 v, r l = 10 k) t a = +25 c t a = t low to t high (note 3) a vol 50 25 500 ? ? ? v/mv output voltage swing v cc = +5.0 v, v ee = 0 v, r l = 10 k, t a = +25 c v cc = +15 v, v ee = ?15 v, r l = 10 k, t a = +25 c v cc = +15 v, v ee = ?15 v, r l = 10 k, t a = t low to t high (note 3) v oh 3.5 13.6 13.3 4.3 14.2 ? ? ? ? v v cc = +5.0 v, v ee = 0 v, r l = 10 k, t a = +25 c v cc = +15 v, v ee = ?15 v, r l = 10 k, t a = +25 c v cc = +15 v, v ee = ?15 v, r l = 10 k, t a = t low to t high (note 3) v ol ? ? ? 0.05 ?14.2 ? 0.15 ?13.6 ?13.3 output short circuit (t a = +25 c) input overdrive = 1.0 v, output to ground source sink i sc 3.0 15 5.0 27 ? ? ma input common mode voltage range t a = +25 c t a = t low to t high (note 3) v icr v ee to (v cc ?1.8) v ee to (v cc ?2.2) v common mode rejection ratio (r s 10 k), t a = +25 c cmrr 80 90 ? db power supply rejection ratio (r s = 100 ), t a = +25 c psrr 80 100 ? db power supply current (per amplifier) v cc = +5.0 v, v ee = 0 v, t a = +25 c v cc = +15 v, v ee = ?15 v, t a = +25 c v cc = +15 v, v ee = ?15 v, t a = t low to t high (note 3) i d ? ? ? 180 220 ? 250 250 300 a 1. either or both input voltages must not exceed the magnitude of v cc or v ee. 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded. 3. mc3317x t low = ?40 ct high = +85 c mc3317xv t low = ?40 ct high = +125 c
mc33171, mc33172, mc33174 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = ?15 v, r l connected to ground, t a = +25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v in = ?10 v to +10 v, r l = 10 k, c l = 100 pf) a v +1 a v ?1 sr 1.6 ? 2.1 2.1 ? ? v/ s gain bandwidth product (f = 100 khz) gbw 1.4 1.8 ? mhz power bandwidth a v = +1.0 r l = 10 k, v o = 20 v pp , thd = 5% bwp ? 35 ? khz phase margin r l = 10 k r l = 10 k, c l = 100 pf m ? ? 60 45 ? ? deg gain margin r l = 10 k r l = 10 k, c l = 100 pf a m ? ? 15 5.0 ? ? db equivalent input noise voltage r s = 100 , f = 1.0 khz e n ? 32 ? nv/ hz equivalent input noise current (f = 1.0 khz) i n ? 0.2 ? pa/ hz differential input resistance v cm = 0 v r in ? 300 ? m input capacitance c in ? 0.8 ? pf total harmonic distortion a v = +10, r l = 10 k, 2.0 v pp v o 20 v pp , f = 10 khz thd ? 0.03 ? % channel separation (f = 10 khz) cs ? 120 ? db open loop output impedance (f = 1.0 mhz) z o ? 100 ? figure 2. input common mode voltage range versus temperature figure 3. split supply output saturation versus load current v , input co mm o n m o de v o lta g e ran g e (v) icr t a , ambient temperature ( c) v cc v cc /v ee = 1.5 v to 22 v v io = 5.0 mv v, output saturation voltage (v) sat i l , load current ( ma) source sink v ee v cc v ee v cc /v ee = 5.0 v to 22 v t a = 25 c 0 -2.4 0.1 0 -0.8 -1.6 0 -1.0 1.0 0 -55 -25 0 25 50 75 100 125 0 1.0 2.0 3.0 4.0
mc33171, mc33172, mc33174 http://onsemi.com 5 1. t a = -55 c 2. t a = 25 c 3. t a = 125 c dual quad 1 2 3 single 3 2 1 1 2 3 v cc /v ee = 15 v a v = +1.0 r l = 10 k c l = 100 pf t a = 25 c a v = 1000 a v = 100 a v = 10 a v = 1.0 figure 4. open loop voltage gain and phase versus frequency figure 5. phase margin and percent overshoot versus load capacitance figure 6. normalized gain bandwidth product and slew rate versus temperature figure 7. small and large signal transient response figure 8. output impedance and frequency figure 9. supply current versus supply voltage 0 0 5.0 s/div 50 mv/div 10 v/div 5.0 s/div f, frequency (hz) , excess pahse (degrees) f 1 2 3 4 120 140 160 180 200 220 , open loop voltage gain (db) vol gain margin = 15 db phase margin = 58 v cc /v ee = 15 v r l = 10 k v out = 0 v t a = 25 c 1 - phase 2 - phase, c l = 100 pf 3 - gain 4 - gain, c l = 100 pf m, phase margin (degrees) f c l , load capacitance (pf) 70 60 50 40 30 20 10 %, percent overshoot % m 0 v cc /v ee = 15 v a vol = +1.0 r l = 10 k v o = 20 mv pp t a = 25 c t a , ambient temperature ( c) gbw and sr (normalized) gbw sr v cc /v ee = 15 v r l = 10 k f, frequency (hz) z , output impedance () w o v cc /v ee , supply voltage ( v) d i, i, power supply current (ma) cc a 3 0 20 10 0 -10 -20 -30 70 60 50 40 30 20 10 0 1.3 1.2 1.1 1.0 0.9 0.8 0.7 140 120 100 80 60 40 20 0 1.1 0.9 0.7 0.5 0.3 0.1 100 k 1.0 m 10 m 10 20 50 100 200 500 1.0 k -55 -25 0 25 50 75 100 125 200 2.0 k 20 k 200 k 2.0 m 0 5.0 10 15 20 25 v cc /v ee = 15 v v cm = 0 v v o = 0 v i o = 0.5 ma t a = 25 c
mc33171, mc33172, mc33174 http://onsemi.com 6 applications information ? circuit description/performance features although the bandwidth, slew rate, and settling time of the mc33171/72/74 amplifier family is similar to low power op amp products utilizing jfet input devices, these amplifiers offer additional advantages as a result of the pnp transistor differential inputs and an all npn transistor output stage. because the input common mode voltage range of this input stage includes the v ee potential, single supply operation is feasible to as low as 3.0 v with the common mode input voltage at ground potential. the input stage also allows differential input voltages up to 44 v, provided the maximum input voltage range is not exceeded. specifically, the input voltages must range between v cc and v ee supply voltages as shown by the maximum rating table. in practice, although not recommended, the input voltages can exceed the v cc voltage by approximately 3.0 v and decrease below the v ee voltage by 0.3 v without causing product damage, although output phase reversal may occur. it is also possible to source up to 5.0 ma of current from v ee through either inputs' clamping diode without damage or latching, but phase reversal may again occur. if at least one input is within the common mode input voltage range and the other input is within the maximum input voltage range, no phase reversal will occur. if both inputs exceed the upper common mode input voltage limit, the output will be forced to its lowest voltage state. since the input capacitance associated with the small geometry input device is substantially lower (0.8 pf) than that of a typical jfet (3.0 pf), the frequency response for a given input source resistance is greatly enhanced. this becomes evident in d?to?a current to voltage conversion applications where the feedback resistance can form a pole with the input capacitance of the op amp. this input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. in this context, lower input capacitance is desirable especially for higher values of feedback resistances (lower current dacs). this input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. for 10 k of feedback resistance, the mc33171/72/74 family can typically settle to within 1/2 lsb of 8 bits in 4.2 s, and within 1/2 lsb of 12 bits in 4.8 s for a 10 v step. in a standard inverting unity gain fast settling configuration, the symmetrical slew rate is typically 2.1 v/ s. in the classic noninverting unity gain configuration the typical output positive slew rate is also 2.1 v/ s, and the corresponding negative slew rate will usually exceed the positive slew rate as a function of the fall time of the input waveform. the all npn output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional npn/pnp transistor class ab output stage. a 10 k load resistance can typically swing within 0.8 v of the positive rail (v cc ) and negative rail (v ee ), providing a 28.4 vpp swing from 15 v supplies. this large output swing becomes most noticeable at lower supply voltages. the positive swing is limited by the saturation voltage of the current source transistor q7, the v be of the npn pull?up transistor q17, and the voltage drop associated with the short circuit resistance, r5. for sink currents less than 0.4 ma, the negative swing is limited by the saturation voltage of the pull?down transistor q15, and the voltage drop across r4 and r5. for small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of v ee . for sink currents (> 0.4 ma), diode d3 clamps the voltage across r4. thus the negative swing is limited by the saturation voltage of q15, plus the forward diode drop of d3 ( v ee +1.0 v). therefore an unprecedented peak?to?peak output voltage swing is possible for a given supply voltage as indicated by the output swing specifications. if the load resistance is referenced to v cc instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. for light load currents, the load resistance will pull the output to v cc during the positive swing and the output will pull the load resistance near ground during the negative swing. the load resistance value should be much less than that of the feedback resistance to maximize pull?up capability. because the pnp output emitter?follower transistor has been eliminated, the mc33171/72/74 family offers a 15 ma minimum current sink capability, typically to an output voltage of (v ee +1.8 v). in single supply applications the output can directly source or sink base current from a common emitter npn transistor for current switching applications. in addition, the all npn transistor output stage is inherently faster than pnp types, contributing to the bipolar amplifier's improved gain bandwidth product. the associated high frequency low output impedance (200 typ @ 1.0 mhz) allows capacitive drive capability from 0 pf to 400 pf without oscillation in the noninverting unity gain configuration. the 60 phase margin and 15 db gain mar gin, as well as the general gain and phase characteristics, are virtually independent of the source/sink output swing conditions. this allows easier system phase compensation, since output swing will not be a phase consideration. the ac characteristics of the mc33171/72/74 family also allow excellent active filter capability, especially for low voltage single supply applications. although the single supply specification is defined at 5.0 v, these amplifiers are functional to at least 3.0 v @ 25 c. however slight changes in parametrics such as bandwidth, slew rate, and dc gain may occur.
mc33171, mc33172, mc33174 http://onsemi.com 7 if power to this integrated circuit is applied in reverse polarity, or if the ic is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. as usual with most high frequency amplifiers, proper lead dress, component placement and pc board layout should be exercised for optimum frequency performance. for example, long unshielded input or output leads may result in unwanted input/output coupling. in order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. this not only minimizes the input pole for optimum frequency response, but also minimizes extraneous apick upo at this node. supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. the output of any one amplifier is current limited and thus protected from a direct short to ground. however, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. t ypically for 15 v supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.
mc33171, mc33172, mc33174 http://onsemi.com 8 figure 10. ac coupled noninverting amplifier with single +5.0 v supply figure 11. ac coupled inverting amplifier with single +5.0 v supply figure 12. dc coupled inverting amplifier maximum output swing with single +5.0 v supply figure 13. offset nulling circuit figure 14. active high?q notch filter figure 15. active bandpass filter 2.2 k 510 k v cc 100 k c in v in 1.0 k + - c o v o 3.6 vpp a v = 101 bw ( -3.0 db) = 20 khz v o 0 100 k 100 k v cc 100 k c o v o + - 10 k c in v in a v = 10 bw ( -3.0 db) = 200 khz 10 k 100 k 100 k v cc 50 k r l 4.7 k + - 100 k 1.0 m v o v in 4.2 vpp v o 2.5 v a v = 10 bw ( -3.0 db) = 200 khz v cc 7 3 6 2 5 1 4 10 k v ee + - offset nulling range is approximately 80 mv with a 10 k potentiometer, mc33171 only. v in - + v o 0.01 2c 0.02 2r 32 k f o = 1.0 khz f o = 1 4 p rc v in 0.2 vdc 2c 0.02 16 k 16 k v in r1 1.1 k r2 5.6 k r3 2.2 k - + v o c 0.047 0.4 v cc f o = 30 khz q = 10 h o = 1.0 r1 = r3 2 h o r2 = r3 = q f o c r1 r3 4q 2 r1 -r3 q o f o gbw < 0.1 given f o = center frequency a o = gain at center frequency choose value f o , q, a o , c for less than 10% error for operational amplifier, where f o and gbw are expressed in hz. c 0.047 rl 100 k rl r c r v cc then: 3.8 vpp v o 0
mc33171, mc33172, mc33174 http://onsemi.com 9 ordering information op amp function device operating temperature range package shipping 2 single mc33171d MC33171DR2 mc33171p t a = ?40 to +85 c so?8 so?8/tape & reel plastic dip 98 units/rail 2500 units/tape & reel 50 units/rail dual mc33172d mc33172dg mc33172dr2 mc33172dr2g mc33172p t a = ?40 to +85 c so?8 so?8 so?8/tape & reel so?8/tape & reel plastic dip 98 units/rail 98 units/rail 2500 units/tape & reel 2500 units/tape & reel 50 units/rail mc33172vd mc33172vdr2 t a = ?40 to +125 c so?8 so?8/tape & reel 98 units/rail 2500 units/tape & reel quad mc33174d mc33174dr2 mc33174dr2g mc33174dtb mc33174dtbr2 mc33174p t a = ?40 to +85 c so?14 so?14/tape & reel so?14/tape & reel tssop?14 tssop?14/tape & reel plastic dip 55 units/rail 2500 units/tape & reel 2500 units/tape & reel 96 units/rail 2500 units/tape & reel 25 units/rail mc33174vdr2 mc33174vp t a = ?40 to +125 c so?14/tape & reel plastic dip 2500 units/tape & reel 25 units/rail 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc33171, mc33172, mc33174 http://onsemi.com 10 marking diagrams pdip?8 p suffix case 626 1 8 x = 1 or 2 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so?8 d suffix case 751 alyw 3317x 1 8 so?8 vd suffix case 751 alyw 3172v 1 8 pdip?14 p suffix case 646 1 14 mc33174p awlyyww pdip?14 vp suffix case 646 so?14 d suffix case 751a 1 14 mc33174d awlyww so?14 vd suffix case 751a tssop?14 dtb suffix case 948g mc3317xp awl yyww 1 14 mc33174vp awlyyww 1 14 mc33174vd awlyww 1 14 mc33 174 alyw
mc33171, mc33172, mc33174 http://onsemi.com 11 package dimensions pdip?8 p suffix case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040
mc33171, mc33172, mc33174 http://onsemi.com 12 so?8 d, vd suffix case 751?07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standard is 751-07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m figure 16. so?8 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mc33171, mc33172, mc33174 http://onsemi.com 13 package dimensions pdip?14 p, vp suffix case 646?06 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ?t? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 so?14 d, vd suffix case 751a?03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc33171, mc33172, mc33174 http://onsemi.com 14 package dimensions tssop?14 dtb suffix case 948g?01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? ??? section n-n detail e j j1 k k1 detail e f m -w- 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc33171/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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